1. Field of the Invention
The present invention relates to a band-gap reference voltage generator for low-voltage operation and high precision, and more particularly, to a band-gap reference voltage generator for low-voltage operation and high precision which is relatively unaffected by offset noise and capable of providing stable reference voltage even at a power supply voltage of 1V or less.
This work was partly supported by the IT R&D program of MIC/IITA [2006-S006-02, Part/Module for ubiquitous terminal].
2. Discussion of Related Art
In general, all analog/radio frequency (RF) or digital circuits integrated into a chip need a stable, precise bias voltage for efficient operation.
However, the bias voltage provided by a typical bias circuit deviates from a constant value over time due to change in the temperature of the bias circuit during operation.
For this reason, a band-gap reference voltage generator is used to provide a stable reference voltage in spite of temperature change using the temperature dependence of a bipolar transistor (or diode).
FIG. 1 is a circuit diagram of a known complementary metal oxide semiconductor (CMOS) band-gap reference voltage generator.
Referring to FIG. 1, the known CMOS band-gap reference voltage generator comprises first, second and third p-channel metal oxide semiconductor (PMOS) transistors M1, M2 and M3, a feedback amplifier AMP, first and second resistors R1 and R2, and first, second and third bipolar transistors Q1, Q2 and Q3.
Here, a first node voltage −Vin and a second node voltage +Vin have the same value due to virtual ground of the feedback amplifier AMP. More specifically, when the first node voltage −Vin is lower than the second node voltage +Vin, an output voltage of the feedback amplifier AMP is increased, and thus current flowing to the first resistor R1 is decreased. The decreased current flows to the second bipolar transistor Q2, and thus the second node voltage +Vin is decreased. In contrast, when the first node voltage −Vin is higher than the second node voltage +Vin, the output voltage of the feedback amplifier AMP is decreased, and thus current flowing to the first resistor R1 is increased. The increased current flows to the second bipolar transistor Q2, and thus the second node voltage +Vin is increased.
A reference voltage Vref output from the band-gap reference voltage generator configured in this way is unaffected by changes in temperature, as explained mathematically below.
Since the feedback amplifier AMP has the same voltages +Vin and −Vin across its inputs due to its virtual ground, the second node voltage +Vin is equal to a base-emitter voltage VBE1 of the first bipolar transistor Q1. Thus, the voltage applied to the first resistor R1 is as follows: ΔVBE=VBE1−VBE2. When converted with respect to temperature, the voltage ΔVBE can be expressed as in Equation 1 below.
                                                                        Δ                ⁢                                                                  ⁢                                  V                  BE                                            =                            ⁢                                                V                                      BE                    ⁢                                                                                  ⁢                    1                                                  -                                  V                                      BE                    ⁢                                                                                  ⁢                    2                                                                                                                          =                            ⁢                                                                    V                                          T                      ⁢                                                                                                                            ⁢                  ln                  ⁢                                                                          ⁢                                                            I                                              C                        ⁢                                                                                                  ⁢                        1                                                                                    I                                              S                        ⁢                                                                                                  ⁢                        1                                                                                            -                                                      V                    T                                    ⁢                                                                          ⁢                  ln                  ⁢                                                                                                                                ⁢                                              n                        ·                                                  I                                                      C                            ⁢                                                                                                                  ⁢                            2                                                                                                                                      I                                              S                        ⁢                                                                                                  ⁢                        2                                                                                                                                                                    =                            ⁢                                                V                  T                                ⁢                                                                  ⁢                ln                ⁢                                                                  ⁢                n                                                                        Equation        ⁢                                  ⁢        1            
Here, Is is a saturation current which is proportional to the number of bipolar transistors, Ic is a current flowing to the bipolar transistor, n is the number of bipolar transistors, and VT is a thermal voltage that has a value of about 25 mV at room temperature.
In Equation 1, the natural logarithm of the number of bipolar transistors (ln n) is a constant, and thus the rate of change of ΔVBE with respect to temperature can be expressed as in Equation 2 below.
                                                        ∂              Δ                        ⁢                                                  ⁢                          V              BE                                            ∂            T                          ≈                              ∂                          V              T                                            ∂            T                          ≈                              +            0.087                    ⁢                                          ⁢                      mV            /                                         °                                ⁢                                          ⁢                      C            .                                              Equation        ⁢                                  ⁢        2            
The voltage ΔVBE applied to the first resistor R1 increases in direct proportion to temperature. The current I2 flowing to the resistor R1 is mirrored to the third PMOS transistor M3 with the temperature dependence of ΔVBE copied without a change. The mirrored current I3 flows to the second resistor R2 and the third bipolar transistor Q3.
Here, the rate of change of the base-emitter voltage VBE3 of the third bipolar transistor Q3 with respect to temperature can be expressed as in Equation 3.
                                          ∂                          V                              BE                ⁢                                                                  ⁢                3                                                          ∂            T                          ≈                              -            1.5                    ⁢                                          ⁢                      mV            /                                         °                                ⁢                                          ⁢                      C            .                                              Equation        ⁢                                  ⁢        3            
As can be seen from Equation 3, the base-emitter voltage VBE3 of the third bipolar transistor Q3 decreases in proportion to temperature.
Thus, since the voltage applied to the resistor R2 increases in proportion to temperature, and since the base-emitter voltage VBE3 of the third bipolar transistor Q3 decreases in proportion to temperature, the reference voltage Vref generated by the sum of the two voltages is unaffected by a change in temperature. The reference voltage Vref can be expressed as in Equation 4.
                              V          ref                =                                            V                              BE                ⁢                                                                  ⁢                3                                      +                                                            R                  2                                                  R                  1                                            ⁢                              V                T                            ⁢              ln              ⁢                                                          ⁢              n                                ≈                      1.25            ⁢                                                  ⁢            V                                              Equation        ⁢                                  ⁢        4            
As can be seen from Equation 4, VBE3 decreases in proportion to temperature, and VT increases in proportion to temperature. As such, when a resistance ratio of the first and second resistors R1 and R2 is properly adjusted, the reference voltage Vref can be held constant despite temperature change.
As described above, the known band-gap reference voltage generator configured as in FIG. 1 cannot be applied to a circuit design for an applied voltage of 1V or less, because the theoretical reference voltage Vref has a perfect temperature compensation characteristic in the proximity of about 1.25V, as shown by Equation 4. Furthermore, a power supply of at least 1.5V is required to guarantee smooth operation of the transistors used in the reference voltage generator.
Mobile communication terminals which have attracted the most attention in recent years employ a low-power consumption design for a core chip in order to achieve portability and long battery life.
However, the problem with applying a low supply voltage for the low-power consumption design is that a band-gap bias circuit functioning as a core in the chip needs a working power supply of at least 1.5V, as described above.
An input stage of the feedback amplifier AMP of FIG. 1 is generally designed with two CMOS transistors. Although the two CMOS transistors have identical designs, it is difficult to fabricate them to have exactly the same characteristics due to process fluctuations. This characteristic difference between the transistors causes an offset. In this case, the first node voltage −Vin and the second node voltage +Vin have different magnitudes, so that a precise reference voltage cannot be generated.